1. Field of the Invention
The present invention relates to an apparatus and method for interrupt processing, and more particularly to an apparatus and method for interrupt processing in which an interrupt is latched in a synchronous system in order to process the interrupt of a code division multiple access, (CDMA) switching apparatus and an interrupt of higher priority order is processed by arbitrarily designating the priority order of the interrupt, and then, an interrupt of lower priority order is processed in order regardless of the priority order.
2. Description of Related Art
As shown in FIG. 1, a conventional interrupt processing apparatus comprises an interrupt input portion 1 for inputting a plurality of interrupts, an interrupt controller 2 for selectively outputting an interrupt of higher priority order from a plurality of interrupts input concurrently from interrupt input portion 1, and an interrupt processor 3 for processing the interrupt selected at interrupt controller 2.
In the conventional interrupt processing apparatus of this configuration, when a new interrupt is input to interrupt input portion 1, the priority order of the newly input interrupt is compared with that of the interrupt currently in action at interrupt controller 2. If the priority order of the newly input interrupt is lower than that of the interrupt in action, the currently acting interrupt continues. In the reverse case, the interrupt in action is halted and the new interrupt of higher priority order is processed at interrupt processor 3.
However, the conventional interrupt processing apparatus of this configuration operates only to interrupt requests of a higher level, so that the apparatus cannot be applied to a control system in a code division multiple access, (CDMA) switching apparatus to which an interrupt having no priority order is applied.
An interrupt processing apparatus is disclosed in U.S. Pat. No. 5,197,083. The technology disclosed therein relates to an art in which a higher priority order interrupt input halts a currently operating interrupt and then the interrupt of higher priority order is carried out. Accordingly, the technology cannot be applied to a code division multiple access apparatus to which an interrupt having no priority order is applied.